Vitro Shard

Vitro Shard

Vitro Shard (v2.0) is a Computer on Module that delivers an edge to cloud hardware and software solution to secure data from sensors, scanners, scales, and meters in-transit and at-rest in the cloud. Vitro IoT Block libraries enable rapid development of applications serving authenticated data payloads via Zero Trust policies. Its codebase is written in MbedOS/C++ and includes libraries for OTA, AWS IoT integration, ECC authentication, and sample projects. Vitro Shard is built in half mini PCIe form factor for easy integration into other projects.

It is compatible with Vitro Crystal gateway from the local CAN bus to Vitro Cloud infrastructure, and supports over-the-air update services. It comes in mini PCIe card format.

Overview

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Vitro Shard.

The Vitro Shard has mainly two elements: STM32L486RG MCU and ATECC608A. The device also has up to 8x Analog Input channels 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps. Regarding digital inputs, it supports CAN (2.0B Active), SPI, USB (OTG 2.0 full-speed, LPM and BCD), 2x I2C, and 3x UART.

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Please refer to the Pinout mapping table for more details.

As an example of a typical application for Vitro Shard, you can check the following image:

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Typical Vitro Shard application.

MCU

The STM32L486RG is an ultra-low-power microcontroller based on the high-performance Arm Cortex-M4 32-bit RISC core. It operates at a frequency of up to 80 MHz, and has 128KB SRAM, 1 MB flash, two banks read-while-write for remote OTA, true random number generator, and AES 256-bit key encryption hardware accelerator.

The Cortex-M4 core features a Floating point unit (FPU) single precision, which supports all Arm single-precision data-processing instructions and data types and implements a full set of DSP instructions and a memory protection
unit (MPU), which enhances application security.

Depending on the selected power-saving mode, different power consumption levels on the CPU unit can be achieved, as low as 420 nA Standby mode with RTC.

The AES hardware accelerator can be used to encipher and decipher data, supports 128-bit block cipher, and the following block cipher mode: ECB, CBC, CTR, GCM, GMAC, and CMAC.

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You can learn more by reading the MCU's datasheet and the reference manual.

A simplified block diagram is shown below:

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Simplified Vitro Shard MCU diagram.

System Memory Boot Mode

The bootloader primary purpose is to download the application program to the internal Flash memory through a serial communication channel. It is stored in the internal boot ROM of any STM32 device.

This means that if you want to flash the MCU via USB or other serial peripheral, it is necessary to enter into bootloader mode. Each serial interface and MCU has its communication protocol. You can obtain this configuration by checking system memory boot mode documentation. Note that the MCU used on Vitro Shard is STM32L486RG, this means that it is in the STM32L47xxx/48xxx family. Information regarding the bootloader of these devices is located in chapter 62, page 328. There, you can verify that the bootloader is activated by applying Pattern 7, which is described in Table 2. The following table is an excerpt from Table 2:

PatternCondition
Pattern 7Boot0(pin) = 1, nBoot1(bit) = 1 and BFB2(bit) = 0
Pattern 7Boot0(pin) = 0, BFB2(bit) = 1 and both banks do not contain valid code
Pattern 7Boot0(pin) = 1, nBoot1(bit) = 1 and BFB2(bit) = 1

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Different boot modes can be selected through BOOT0 pin, boot configuration is set by nBoot1 bits, and BFB2 bit selects boot from Flash memory bank 2.

On Vitro Shard, you can set these pins in the following way:

  • BOOT0 pin should be physically connected with the 3.3V pin output. Vitro Shard Edge has these two pins available on the J64 header.
  • The Option Byte'nBoot1' bits are set to 1 by default, so no configuration is needed.
  • The Option Byte'BFB2' bits can be either 0 or 1; thus, no further actions are needed.

Another important aspect is to connect the serial peripheral correctly with the MCU. For the USB connection, we need to connect it as shown in Table 133 on the DFU bootloader section (found on the system memory boot mode documentation). You can check the USB DFU protocol for this bootloader here.

Secure Boot

You can implement secure boot using Vitro Shard. There are many implementation steps; however, you also need to configure the MCU to make the bootloader immutable, thus becoming the Root of Trust. The necessary configuration is as follows:

  • Option bytes must be set to enable Readout protection to level 2.

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This can be done by following the instructions in section 3.5.1 in the reference manual.

  • Option bytes must be set to configure the bootloader's memory area as Write Protected.

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The MCU allows you to set a start and end offset to the write-protected area (up to two). The Option Bytes are WRPxA_STRT and WRPxA_END, where x can be either 1 or 2. For more information, check section 3.5.3 in the reference manual.

  • Option bytes must be set to enable booting from flash memory only.

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For instructions, please check section 2.6.1 in the reference manual.

These changes will make Vitro Shard always boots from flash memory and hence bootloader. The bootloader can't be changed or erased, but the remaining flash memory can still be reprogrammed.

ST-LINK

The MCU also supports ST-LINK, which is an in-circuit debugger and programmer. There is no SWD header for Vitro Shard; however, it is available on the device. To do that, you need to add a 2x10 1.27mm male pin header on J38 (FTSH style). Now you can make an SWD connection. As an example, the wiring diagram between Vitro hard and Nucleo L476RG is as follows:

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Connection between Vitro Shard and the Nucleo's ST-LINK.

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For more information regarding the FTSH style header, you can read the datasheet.

It is recommended that you read ST-LINK utility software documentation, and the user manual.

ECC

The Microchip ATECC608A is a cryptographic co-processor. It integrates ECDH security protocol and ECDSA sign-verify authentication. ATECC608A also has an integrated AES hardware acceleration and enables secure boot capabilities for some MCUs. It also supports autonomous PKI key generation and storage for up to 16 keys, certificates, and data.

There is also hardware support for asymmetric sign, verify, and key agreement; and for symmetric algorithms (e.g., SHA-256 and AES-128). The chip offers full ECDSA code signature validation and optional stored digest/signature for secure boot. There are security features to better protect from attacks: optional communication key disablement prior to secure boot, and encryption/authentication for messages to prevent onboard attacks.

There are many differences between Vitro Crystal's ATECC508A and Vitro Shard's ATECC608A. They are listed in sections 3.1.1 and 3.1.2 of the ATECC608A Data Sheet.

Ratings

The ratings of the device are as follows:

ParameterSymbolMinMaxUnit
Supply VoltageVDD-0.34.0V
FT GPIO Input VoltageFT GPIO VIN-0.3VDD + 4.0V
TT GPIO Input VoltageTT GPIO VIN-0.34.0V
BOOT0 PinVN BOOT0-0.39V
Operating Ambient TemperatureTAMB-4085°C

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Stresses above the absolute maximum ratings listed above may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

Specifications apply for –40°C < TPCB < 85°C, unless otherwise noted.

ParameterSymbolMinTypicalMaxUnit
Supply VoltageVDD2.03.33.6V
FT GPIO Input VoltageFT_VIN5.5V
TT GPIO Input VoltageTT_VIN3.6V
Voltage Input HighVIH0.7VDDV
Voltage Input LowVIL0.39VDDV
Voltage Output HighVOHVDD - 0.44V
Voltage Output LowVOL0.4V

Pinout

The pinout tables are:
Power

Pin #Net NamePin StyleSTM32 Pin #STM32 Pin NameAlternate FunctionIO Voltage Group
2, 24, 39, 41, 523V3PWR
4, 9, 18, 26, 34, 35, 37, 40, 50GNDGND

NC

Pin #Net NamePin StyleSTM32 Pin #STM32 Pin NameAlternate FunctionIO Voltage Group
11, 13, 16, 23, 25, 31, 33NOT CONNECTEDNC

RSVD

Pin #Net NamePin StyleSTM32 Pin #STM32 Pin NameAlternate FunctionIO Voltage Group
22NRSTRSVD
20BOOT0RSVD
43IO_BUF_ENRSVD2PC13OUTPUT/RSVDFT / 5V Tolerant
44IO_BUF_EN HARD_3V3_
EN_N_PC3RSVD11PC3GPIOFT / 5V Tolerant

IO

Pin #Net NamePin StyleSTM32 Pin #STM32 Pin NameAlternate FunctionIO Voltage Group
36USB_OTG_FS_DMUSB45PA12GPIO/USB_DMFT / 5V Tolerant
38USB_OTG_FS_DPUSB44PA11GPIO/USB_DPFT / 5V Tolerant
42USB_OTG_FS_VBUS_PA9USB42PA9GPIO/USB_VBUSFT / 5V Tolerant
21USB_OTG_OVRCR_BUFUSB34PB13INPUTFT / 5V Tolerant
29USB_OTG_PPWR_BUFUSB37PC6OUTPUT/USB_PWR_ENFT / 5V Tolerant
27USB_OTG_PRDY_BUFUSB34PB13INPUTFT / 5V Tolerant
10CAN_RX_BUFGPIO61PB8INPUT/CAN_RXFT / 5V Tolerant
8CAN_TX_BUFGPIO62PB9OUTPUT/CAN_TXFT / 5V Tolerant
28SPI1_MISO/ADC1_IN11GPIO22PA6GPIO/SPI/ADCFT / 5V Tolerant
6SPI1_MISO/ADC1_IN12GPIO23PA7GPIO/SPI/ADCFT / 5V Tolerant
46SPI1_NSS/ADC1_IN9GPIO20PA4GPIO/SPI/ADCFT / 3.6V Tolerant
48SPI1_SCK/ADC1_IN10GPIO21PA5GPIO/SPI/ADCFT / 3.6V Tolerant
7UART_DEBUG_RXGPIO54PD2GPIO/UARTFT / 5V Tolerant
5UART_DEBUG_TXGPIO53PC12GPIO/UARTFT / 5V Tolerant
12UART_RS232_RX_BUFGPIO17PA3INPUT/UARTFT / 5V Tolerant
14UART_RS232_TX_BUFGPIO16PA2OUTPUT/UARTFT / 5V Tolerant
19UART_RS485_DEGPIO27PB1GPIO/UARTFT / 5V Tolerant
15UART_RS485_RXGPIO30PB11GPIO/UARTFT / 5V Tolerant
17UART_RS485_TXGPIO29PB10GPIO/UARTFT / 5V Tolerant
3UART_USER_RX/ADC1_IN6GPIO15PA1GPIO/UART/ADCFT / 5V Tolerant
1UART_USER_TX/ADC1_IN5GPIO14PA0GPIO/UART/ADCFT / 5V Tolerant
51GPIO_PC10GPIO51PC10GPIOFT / 5V Tolerant
49GPIO_PC11GPIO52PC11GPIOFT / 5V Tolerant
30I2C1_SCLGPIO58PB6GPIO/I2CFT / 5V Tolerant
32I2C1_SDAGPIO59PB7GPIO/I2CFT / 5V Tolerant
47I2C3_SCL/ADC1_IN1GPIO8PC0GPIO/I2C/ADCFT / 5V Tolerant
45I2C3_SDA/ADC1_IN2GPIO9PC1GPIO/I2C/ADCFT / 5V Tolerant

Pinout Details

GPIO Pin TypeAvailable Pins within this GroupDescription
GPIO2General Purpose Input/Output pin – can work either as an output or input
GPIO DIG9Pins from this group can work as a regular GPIO or can work as specific interface lines (SPI/I2C/UART) – refer to pinout mapping table for Digital interfaces location details
GPIO ADC8Pins from this group can work as a regular GPIO or can work as Analog Input pin to ADC
CAN3Pins from this group can work as a regular GPIO or can work as CAN TX/RX interface lines – refer to pinout mapping table for Digital interfaces location details
USB2Pins from this group can work as a regular GPIO or can work as a USB DP/DN differential pair – refer to pinout mapping table for location details
USB CTRL3Pins from this group can work as a regular GPIO or can work as USB CTRL lines together with USB differential pair – refer to pinout mapping table for location details
RSVD4Internal IO buffer enable, STM32 NRST, STM BOOT lines

Specifications

NameDescription
MicrocontrollerARM Cortex-M4 STM32L4 @ 80 MHz
MCU Memory1 MB (1M x 8) FLASH
Security ICATECC608A-MAHDA-T
USB OTG1
UART Interface1x dedicated for RS-485 connection on carrier card
UART Interface1x dedicated for RS-232 connection on carrier card
UART Interface1x dedicated for Debug interface on carrier card
UART Interface1x dedicated for user usage (switchable UART/ADCIN)
SPI Interface1x dedicated for user usage (switchable UART/ADCIN)
I2C Interface1x dedicated for user usage (switchable I2C/ADCIN)
I2C Interface1x dedicated for internal usage
Status LEDs1
I/O10X GPIO PINS (multifunction pins: GPIO/I2C/SPI/UART/ADC)
Power Input3.3V DC via miniPCIE slot
Temperature RangeCommercial: 0°C to 85°C
Temperature RangeIndustrial: -40°C to 100°C (optional)
Mechanical/Board SizeStandard Half-size mini-PCIe board size

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